Hi. I'm Shivangi Gambhir.

I am currently residing in New Delhi. I completed my high school from Kalpa Co-Educational School,Hyderabad and finished my secondary school from FIITJEE,Hyderabad. I completed my undergraduate studies in the Electronics and Communication Engineering department from Manipal Institute of Technology,Manipal.

I am currently a Masters/Graduate student at Cornell University specializing in the Electrical and Computer Engineering Discipline. My inquisitiveness and immense passion in Computer Architecture and Chip Designing has led me to actively work and contribute on related projects. With two years work experience in Qualcomm and the skills I'll be honing at Cornell, I look forward to explore/work in the world of chips & processors.

Experience

Worked as an Associate Engineer, in the Memory IP team in the Front End Views division in Qualcomm India from July 2017 - July 2019

My major work comprised of Behavioral Modelling of the Memories and Design Verification. Modelling of the memory required hands on working with verilog and verification comprised of both functional verification using the testbenches written by the team and formal verification using the ESPCV tool.

I actively contributed in projects dealing with lower technology nodes. I gained expertise in designing and developing failure analysis files that were used to check the physical to logical address mapping of the memories.

Besides this, development of new quality checks using PERL scripting for the deliverables were an additional part of the work.I also submitted a technical paper, along with other teammates, in “QBUZZ”. The paper was titled “At-speed test coverage improvement using ram writethrough models”.

As a Project Intern in the Wireless Network Sensor Lab at Indian Institute of Science,Bangalore,India from February 2017 to June 2017

Worked on a project "Intrusion detection using PIR sensors and Video Camera" at the Wireless Sensor Network Lab along with other lab members
Learned working of PIR sensors and Lucas Kanade Optical Flow Algorithm to detect moving objects.

As an Industrial Trainee in the Defense Research and Development Laboratory for two months

Implemented 1-D interpolation of data using VHDL Language for FPGA.
The algorithm was simulated and produced satisfactory results when compared with the results on MATLAB.

Skill set

Technologies

System verilog, verilog, PERL, Python, VHDL , Basic Shell Scripting

Tools

ESPCV, Virtuoso, Modelsim, VCS, MATLAB, GTKWave , NWave

Platforms and OS

Raspberry Pi, Arduino, 8051, ATMEGA16, Raspbian, Linux, Windows

Projects

Telepresence Robot

A Telepresence Robot is a videoconferencing bot that revolutionizes the way you feel. It enables people to be at more than one place at a single time. This robot which is placed in a remote location is capable to capture the environment in virtual form using Raspberry Pi. The captured visuals are displayed on a webpage and virtual reality headset. The robot present in the remote location can be maneuvered by the user using their smartphone. It provides a real time repsonse to the users head movement using the android phone as an Inertial Measurement Unit(IMU) module.

Iterative Integer Multiplier

An iterative multiplier is designed to carry out multiplication of two integers using repeated addition algorithm. The first implementation is a fixed latency multiplier analogous to a single cycle CPU which always requires the same number of cycles to complete one instruction. The second design is a variable-latency implementation that helps to reduce the cycle time by increasing the cycles per instruction making use of the input operands.

Pipelined Processor

In this project, we designed two implementations of 5 staged pipelined processors to execute register-register arithmetic and logical, register-immediate arithmetic and logical,memory,jump and branch instructions through Fetch, Decode, Execute, Memory and Write-back stages. The first design makes use of stalling, and an alternate design that uses bypassing in order to avoid various hazards raised by pipelining.

Blocking Cache

The project is implemented to understand cache principles and to design and evaluate two cache systems. The cache is designed for a total capacity of 256 bytes with 16 cache lines Two cache systems were implemented namely direct-mapped cache and a two-way set-associative cache. In a direct mapped cache structure, the cache is designed having multiple sets with a single cache line in every set. The Set associative cache can be imagined as a n by m matrix. The cache is divided into ‘n’ sets and each set contains ‘m’ cache lines.A memory block is first mapped onto a set and then placed into any cache line of the set.

Multicore system

The purpose of this project is to design a multicore system using four single core processors, private instruction and shared data caches. The multicore system makes use of networks that have been provided beforehand. In this project, we integrate the already designed pipelined processor and set associative caches. The processor was tested for corner cases and Cycles Per Instruction(CPI) was evaluated in each case.

Neural Recording Front End Array

The goal of this project is to build the front-end of a neural recording system, which would take the raw inputs from the brain, pass them through an amplifier to amplify the signals, filter out the extraneous signals using a bandpass filter, and time multiplex the signals sent through the 16 channels to output a desired signal. Meaningful data can be extracted from this output that can contribute to current neuroscience research.

Publications

An Optical-Camera Complement to a PIR Sensor Array

"An Optical-Camera Complement to a PIR Sensor Array for Intrusion Detection and Classification in an Outdoor Environment," 2017 IEEE 42nd Conference on Local Computer Networks Workshops (LCN Workshops), Singapore, 2017, pp. 44-52. doi: 10.1109/LCN.Workshops.2017.63

See Publication

Achievements

Manipal Entrepreneurship Summit

First Prize in a Business Competition at Manipal Entrepreneurship Summit,2016. We pitched the idea for Rentified, a peer to peer platform for renting, and attained the first position.

Video

Love Bytes:20 tales of love

A published author along with 19 other co-authors in Love Bytes. Love Bytes is a tale of 20 different love stories published on October 17th, 2014 (ISBN: 9789384180799)

Know More

The Campus Connect

Was Chief Editor at The Campus Connect.
The Campus Connect is an online nationwide network of students from all backgrounds coming under one umbrella. We write and publish blogs and encourage people to come forth with their experiences.